The more advanced 2nm process is also reported to have made significant progress. The 2nm process will start mass production around 2023 to 2024.

TSMC thinks risk trial production yield in the second half of 2023 can reach 90%. The 3nm and 5nm processes use FinFET. TSMC 2nm process uses a new multi-bridge channel field effect transistor (MBCFET) architecture.

TSMC plans to switch to GAAFET (gate all around) for 2nm chips. FINFET doesn't surround a channel on all sides. GAA surrounds a channel using a Gate. The latter method makes current leakage almost negligible.

The N5 node that TSMC is working with can use 5nm for up to 14 layers. The 3nm process node could deliver up to a 15% hike in power at the same transistor count as 5nm, and up to a 30% reduction in power use (at the same clock speeds and complexity).

Dutch lithography company ASML says that at 3nm, lithography can be used on more than 20 layers.

Intel is lagging TSMC in reducing transistor size. Intel has published a roadmap that reaches 1.4 nanometers in 2029.